Perl Script to comment unwanted clutter added by Yosys to MSP430 Synthesized Netlist

Hello there,

Following is a small perl script that will help you remove all the unwanted clutter produced by the Yosys Synthesis while MSP430 was synthesized in last post.

#Created By - Alok Govind Dadlani
#Purpose - To remove unwanted clutter from the Synthesized Netlist
#OPENS UP THE FILES ONE IN READ MODE AND LATTER IN WRITE DUE TO '>'
open (FILEHANDLE, "/home/cg/root/Synthesized.v");
open (FILENEWHANDLE, ">/home/cg/root/CleanSynth.v");

#PARSES THROUGH ALL LINES IN SYNTHESIZED NETLIST AND CLEANS IT
for $line (<FILEHANDLE>){
    $line =~ s/\/\/\(\* src = "\/home\/alok\/qflow\/MSP430\//\/\/ /;
    print FILENEWHANDLE $line;
    }

Synthesized.v - Contains Synthesized Netlist
CleanSynth.v - Contains the clean netlist

Synthesizing OpenMSP430 using Yosys Synthesis Suite

Hello,

Purpose: To synthesize bigger design openMSP430 using Yosys Synthesis Suite

Problem: Inherently Yosys is unable to synthesize bigger designs and openMSP430 synthesis has faced the following problem while synthesizing
(https://www.reddit.com/r/yosys/comments/4qtq1d/openmsp430_core_throwing_out_assign_statements_in/)

Softwares used: Yosys 0.6, ABC, Ubuntu 14.04 LTE

//This is not a detailed blog, solution to generally faced problem is solved in here

Solution:

Yosys is a very strong and flexible open source tool for synthesis. Inherently it uses ABC for logic optimization and mapping. It has a capability of synthesizing bigger designs off opencores.org directly.Although, people were facing many problems regarding the synthesis and hence I would love to share my solution with everyone through this blog. Hope it helps!

Following design is taken as reference:
http://opencores.org/project,openmsp430,overview

I have written following script for Yosys which might help you. It flawlessly synthesizes MSP430 and gives the following result:

SCRIPT:
#Written by Alok Govind Dadlani (agdadlan at uci dot edu) and Debhrid Gupta (debhridg at uci dot edu)
#Reference - Tim Edward's Qflow

read_liberty -lib -ignore_miss_dir -setattr blackbox /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib
read_verilog /home/alok/qflow/MSP430/source/openMSP430.v
read_verilog /home/alok/qflow/MSP430/source/omsp_dbg.v
read_verilog /home/alok/qflow/MSP430/source/omsp_dbg_uart.v
read_verilog /home/alok/qflow/MSP430/source/omsp_sync_cell.v
read_verilog /home/alok/qflow/MSP430/source/omsp_multiplier.v
read_verilog /home/alok/qflow/MSP430/source/omsp_watchdog.v
read_verilog /home/alok/qflow/MSP430/source/omsp_sfr.v
read_verilog /home/alok/qflow/MSP430/source/omsp_mem_backbone.v
read_verilog /home/alok/qflow/MSP430/source/omsp_execution_unit.v
read_verilog /home/alok/qflow/MSP430/source/omsp_frontend.v
read_verilog /home/alok/qflow/MSP430/source/omsp_clock_module.v
read_verilog /home/alok/qflow/MSP430/source/omsp_clock_gate.v
read_verilog /home/alok/qflow/MSP430/source/omsp_and_gate.v
read_verilog /home/alok/qflow/MSP430/source/omsp_wakeup_cell.v
read_verilog /home/alok/qflow/MSP430/source/omsp_scan_mux.v
read_verilog /home/alok/qflow/MSP430/source/omsp_sync_reset.v
read_verilog /home/alok/qflow/MSP430/source/omsp_alu.v
read_verilog /home/alok/qflow/MSP430/source/omsp_register_file.v

# High-level synthesis
synth
# Map register flops
dfflibmap -liberty /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib
opt

# Map combinatorial cells, standard script
abc -exe /usr/local/share/qflow/bin/yosys-abc -liberty /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib -script +strash;scorr;ifraig;retime,{D};strash;dch,-f;map,-M,1,{D}
setattr -set keep_hierarchy 1 openMSP430

clean -purge

# Output buffering (Very Important)
iopadmap -outpad BUFX2 A:Y -bits

# Cleanup
opt
clean
write_verilog /home/alok/qflow/MSP430/mspalok1.v

RESULTING NETLIST:

 https://drive.google.com/file/d/0B5u2XuRfY2y3Q1J2S0lsZkI0eVk/view?usp=sharing


#It would be great if proper credits are given while using and sharing. Thank you!# 

-Alok Govind Dadlani, Debhrid Gupta

RTL-to-GDS Flow

RTL-to-GDSII using Qflow

Hello,

Are you a fresher to Digital VLSI, seeking to gain some experience before diving in the semiconductor industry?

Here I am today talking about using RTL-to-GDSII conversion for academic projects! I am a beginner and would just like to share my experience so that others don't get struck where I was.

/*

You: Are you drunk, Alok?

I: Surely not!
You: From where will we get access to Cadence Encounter and other proprietary tools?

I: We will use open-source tools!

You: You are totally drunk!

I: No no, I am not drunk trust me. Let's learn how!

*/

Lets cut this crap and get started. First of all, all the credit goes to endless hours and dedication put in by Mr Tim Edwards for his generous work in bringing all sources and binaries of open tools and filling the gaps in between to make this possible.

All credits to Tim Edwards and opencircuitdesign.com. Not only that, from what I could make out he has put tremendous effort in solving queries and problems of people who have tried his tools.

I started working on this when I was required to fabricate a chip for coursework in VLSI Project Design at UC Irvine. Extensive explanations about what is to be done is found on opencircuitdesign.com very easily. But reason behind writing this blog is I wanted to share the problems I faced as a beginner. Throughout the tutorial I have worked on Ubuntu 14.04 LTE Environment.

What am I talking about?

I am talking about the methods and tools to convert high level circuit design in Verilog or VHDL to physical circuit layout. The flow used to follow this is called RTL-to-GDSII conversion.

What is Verilog RTL?

Verilog RTL is basically a design written in Verilog Language which is a high level language. Either written in behavioral or structural form famously. Example of a Multiplexer using verilog code:

//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Design Name : MUX
// File Name   : mux.v

// Function    : Multiplexer
// Coder       : Alok Govind Dadlani
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

module mux(
in_0      , // Mux first input
in_1      , // Mux Second input
select        , // Select input
out      // Mux output
);
//~~~~~~~~~~~~Input Ports~~~~~~~~~~~~~~~
input in_0, in_1, select ;
//~~~~~~~~~~~~Output Ports~~~~~~~~~~~~~~
output out;
//~~~~~~~~~~~~Internal Variables~~~~~~~~
wire  out;
//~~~~~~~~~~~~Code Start~~~~~~~~~~~~~~~

assign out = (select) ? in_1 : in_0;

endmodule //End Of Module mux

What is GDS?

GDSII is the database file format which industry follows as a standard format for exchange of data related to IC layout. It is a binary file format representing planar geometric shapes, text labels, and other information about the layout in hierarchical form.

What is our aim?

To convert RTL to GDSII which means to convert high level behavioral language to physical layout. And this involves a lot of work and using a of tools which Cadence Encounter has somewhat combined into one tool. But for academic purposes we still can learn about this flow and implement it using what Mr Tim Edwards has done.

What tools do we use in the process?

Yosys - A super powerful open source synthesis suite used for RTL Synthesis

ABC - Logic Optimization and Mapping to standard cell libraries (info about standard cell libraries in next paragraph)

Graywolf - Last non-commercial version of TimerWolf which can perform placement but cannot perform detail routing

Qrouter - Detailed routing Program coded up by Mr Tim Edwards to fix the final link in his flow 

Qflow - All these are combined by the robust Qflow Scripts which enable us to have Open-Source Hardware!
Netgen - For LVS Verification
Icarus Verilog -  To simulate netlist
GTKWave - To view netlist

One quick tip while installing the tools, most of the tools have a ./configure scripts which allow you to understand which dependency is not installed in your system.

Which standard cell libraries did you use?

For my project I used open source Standard cell libraries provided by OSU and IIT. (http://vlsiarch.ecen.okstate.edu/flow/)

At the time of writing I worked with version2.7 from osu.

What problems did I face?

1) Qflow 1.0 was not able to synthesize my design because of some problem with tclsh (https://www.reddit.com/r/yosys/comments/45yjip/hey_im_new_to_qflow_and_i_have_an_issue_please/)

So I would suggest you to move on to the new environment has Mr Edwards has suggested in this forum.

2) My LVS was not matching for larger designs. Connecting Vdd and gnd across different levels in the layout manually solved the problem.

After getting help from Mr Harish Athuru (batch-mate) and reading and comparing my SPICE netlists for smaller designs like CLA we realized that the VDD and GND from different levels were not connected and hence the nets failing the LVS were VDD and GND Nets. So my suggestion is after designs are generated connect VDD across all levels and GND across all levels.

What you need to be prepare before you get started with this?

You need to start with a verilog file for your design. I will explain the steps in a crude way with screenshots. It has been very well explained at opencircuitdesign.com but I would like to add snips to make it more clear.

1) Verilog Source File

2) Project Directory Structure

-Verilog file should be included in source directory
-Testbench should be in the root directory

3) After all tools are installed, we should run the tool flow

-This step will invoke the Synthesis, placement and routing tools
-If this step fails, check synth.log and you can debug from there
-Mainly there might be a problem with the verilog file in most cases

4) Once you run this step there are many files auto generated in the root and the other directories. qflow_exec.sh will allow you to run every step by commenting other steps and debug the problem in  an easier way

5) Once you are done with the step above, now you will move on to using Magic to view the layout which we have generated. But wait, there is more to do. Once you are done you will go to layout directory and invoke magic like below:

6) Now to load the abstract LEF views we use following command at the tk interface of magic. For you the path might be different.

          lef read /usr/local/share/qflow/tech/osu035/osu035_stdcells.lef


7) Now load the routed def file using:

          def read /usr/local/share/qflow/project_cla/layout/cla.def


8) Then set the view:

           grid 1.6um 2.0um


9) Now you will save the top level design by using command given below:

         writeall force cla

10) After this you quit magic and say "Yes" that you dont want to save abstract views

11) Now ensure that you have .magicrc file in place in layout directory, start magic without specifying a file to load:

magic -d OGL

Then load the GDS file, and save all of the standard cells:

gds read osu035_stdcells.gds2
writeall force
quit

12) Actually for me the .magicrc file was not automatically generated in layout so I copy and pasted the file manually in the layout directory at the start of the project and also added the command in it manually as given below:

13) Now load the project top level as below:

Using the mouse controls - Left button to place the box and Right button to expand the box around the layout and then pressing 'x' will make the layout more clear and detailed



14) Now connect the VDDs and GND across different levels as done (shabbily!) in the above screenshot. If you don't do this step, your LVS would not match for larger designs where this is required.

15) Save your design:
     
           writeall force cla

16) Generate a SPICE netlist from the design using the following sequence of commands:

extract all
ext2spice scale off
ext2spice renumber off
ext2spice hierarchy on
ext2spice

(More on ext2spice - http://opencircuitdesign.com/magic/commandref/ext2spice.html)
(More on ext2sim - http://opencircuitdesign.com/magic/commandref/ext2sim.html)

17) After this step you will have cla.spice in layout directory and cla.spc in synthesis directory

18) LVS is the step to match these two netlists

(One trick is that if LVS is not matching then you can compare these two files to get to know what is happening and also comp.out in root directory will be of great help)

For doing LVS check we use a tool named 'netgen' and I used netgen 1.5 for my work. Here you go to project top level and invoke netgen and use LVS command as below:

If your LVS is matched then we can proceed to simulation and if not then you will need the above tricks mentioned and also capability to read comp.out report which you can get help by reading below page. 'Interpreting LVS results' might help to be very specific (http://opencircuitdesign.com/netgen/)


19) Now since the LVS is matching we can simulate the netlist using Icarus Verilog tool

You will change to synthesis directory where you will find cla.rtlnopwr.v file generated:

Simulate using iverilog command as follows:

Next step would be as follows:

20) Once you are done you will see vcd file in the synthesis directory which can be used to plot waveforms and manually verify whether your design has been generated properly

We use GTKWave as a waveform viewer.

So this was the procedure to get your chip fabricated in an academic environment using open source tools. I really hope some day there is good support provided to this kind of work and more sophistication is achieved. I really loved working on this and would welcome any suggestions and queries. I would like to help with as much as I know and would love to listen to your comments below. Thank you and have a wonderful time using these. MAY THE SOURCE BE WITH YOU!