Synthesizing OpenMSP430 using Yosys Synthesis Suite

Hello,

Purpose: To synthesize bigger design openMSP430 using Yosys Synthesis Suite

Problem: Inherently Yosys is unable to synthesize bigger designs and openMSP430 synthesis has faced the following problem while synthesizing
(https://www.reddit.com/r/yosys/comments/4qtq1d/openmsp430_core_throwing_out_assign_statements_in/)

Softwares used: Yosys 0.6, ABC, Ubuntu 14.04 LTE

//This is not a detailed blog, solution to generally faced problem is solved in here

Solution:

Yosys is a very strong and flexible open source tool for synthesis. Inherently it uses ABC for logic optimization and mapping. It has a capability of synthesizing bigger designs off opencores.org directly.Although, people were facing many problems regarding the synthesis and hence I would love to share my solution with everyone through this blog. Hope it helps!

Following design is taken as reference:
http://opencores.org/project,openmsp430,overview

I have written following script for Yosys which might help you. It flawlessly synthesizes MSP430 and gives the following result:

SCRIPT:
#Written by Alok Govind Dadlani (agdadlan at uci dot edu) and Debhrid Gupta (debhridg at uci dot edu)
#Reference - Tim Edward's Qflow

read_liberty -lib -ignore_miss_dir -setattr blackbox /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib
read_verilog /home/alok/qflow/MSP430/source/openMSP430.v
read_verilog /home/alok/qflow/MSP430/source/omsp_dbg.v
read_verilog /home/alok/qflow/MSP430/source/omsp_dbg_uart.v
read_verilog /home/alok/qflow/MSP430/source/omsp_sync_cell.v
read_verilog /home/alok/qflow/MSP430/source/omsp_multiplier.v
read_verilog /home/alok/qflow/MSP430/source/omsp_watchdog.v
read_verilog /home/alok/qflow/MSP430/source/omsp_sfr.v
read_verilog /home/alok/qflow/MSP430/source/omsp_mem_backbone.v
read_verilog /home/alok/qflow/MSP430/source/omsp_execution_unit.v
read_verilog /home/alok/qflow/MSP430/source/omsp_frontend.v
read_verilog /home/alok/qflow/MSP430/source/omsp_clock_module.v
read_verilog /home/alok/qflow/MSP430/source/omsp_clock_gate.v
read_verilog /home/alok/qflow/MSP430/source/omsp_and_gate.v
read_verilog /home/alok/qflow/MSP430/source/omsp_wakeup_cell.v
read_verilog /home/alok/qflow/MSP430/source/omsp_scan_mux.v
read_verilog /home/alok/qflow/MSP430/source/omsp_sync_reset.v
read_verilog /home/alok/qflow/MSP430/source/omsp_alu.v
read_verilog /home/alok/qflow/MSP430/source/omsp_register_file.v

# High-level synthesis
synth
# Map register flops
dfflibmap -liberty /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib
opt

# Map combinatorial cells, standard script
abc -exe /usr/local/share/qflow/bin/yosys-abc -liberty /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib -script +strash;scorr;ifraig;retime,{D};strash;dch,-f;map,-M,1,{D}
setattr -set keep_hierarchy 1 openMSP430

clean -purge

# Output buffering (Very Important)
iopadmap -outpad BUFX2 A:Y -bits

# Cleanup
opt
clean
write_verilog /home/alok/qflow/MSP430/mspalok1.v

RESULTING NETLIST:

 https://drive.google.com/file/d/0B5u2XuRfY2y3Q1J2S0lsZkI0eVk/view?usp=sharing


#It would be great if proper credits are given while using and sharing. Thank you!# 

-Alok Govind Dadlani, Debhrid Gupta